1. Field of the Invention
The invention relates to a method for fabricating a semiconductor capacitor, and more specifically to a method for fabricating the capacitor of a stacked dynamic random access memory (DRAM).
2. Description of Related Art
As a basic element of the semiconductor integrated circuit, the capacitor cannot be replaced by other devices. For most of the widely used electronic components, such as DRAM, oscillators, time delay circuitry, and AD/DA converters, a capacitor is definitely required. The capacitor thus holds an important position in semiconductor circuit design.
The fundamental structure of a capacitor includes a dielectric material which isolates two conducting parts, known as electrodes. The capacitance is therefore determined by three physical characteristics of the capacitor structure: thickness of the dielectric material, the surface area of the electrodes, and electronic and mechanical properties of the dielectric material as well as the electrodes.
In a DRAM cell, the substrate area must be minimized or the cell density cannot be increased. The capacitor in the DRAM cell, however, has to increase the electrode area for a high capacitance. A three-dimensional stacked capacitor cell has therefore been developed to satisfy the requirement of a high-density DRAM circuit. The stacked capacitor has a bristle structure over the access device of a DRAM cell, thus having a low soft error rate (SER) and high dielectric constant.
However, the fabrication process of the three-dimensional stacked capacitor is complicated and costly. The method for fabricating a bristle stacked capacitor, as disclosed in Taiwan Patent No. 239234, will be described in accompaniment with FIG. 1A through FIG. 1D.
Referring to FIG. 1A, a silicon substrate 20 is provided. As known to those skilled in the art, a field oxide layer and a transistor including source/drain diffusion regions should be formed on the silicon substrate 20, but they are omitted in the figure for simplicity. The method for fabricating a capacitor includes depositing an oxide layer 23 by chemical vapor deposition (CVD) over the silicon substrate 20. The oxide layer 23 is etched to form a contact window. A polysilicon layer 24 is then formed by the CVD method over the oxide layer 23 and contacts the silicon substrate 20 via the contact window. Another oxide layer 31 and polysilicon layer 32 are then successively formed over the polysilicon layer 24. Moreover, an aluminum layer 33 is formed over the polysilicon layer 32. The aluminum layer 33 and the polysilicon layer 32 are then annealed at a temperature of 400xc2x0 C.-577xc2x0 C. for 10-1000 seconds, thus forming a plurality of silicon grains between polysilicon layer 32 and oxide layer 31.
Referring to FIG. 1B, using the oxide layer 31 as an etch stop, the structure of FIG. 1A is etched by aqua regia (HNO3:HCl=1:3). Silicon grains 32a having a dimension of 500-5000 xc3x85 therefore remain over the oxide layer 31.
Referring to FIG. 1C, the silicon grains 32a are utilized as a mask for etching the oxide layer 31 by the reactive ion etching (RIE) method, thus forming a plurality of oxide islands 31a having a dimension of 500-5000 xc3x85. Moreover, the oxide islands 31a are utilized as a mask for etching the polysilicon layer 24 to a predetermined thickness, thereby forming a plurality of irregular polysilicon pillars.
Referring to FIG. 1D, as the silicon grains 32a and the oxide islands 31a are removed, the polysilicon layer 24 is the lower electrode of a capacitor. The electrode area has therefore been increased by the polysilicon pillars.
The fabricating method described above, however, has very complicated steps and cannot be precisely controlled. For example, the dimensions of the silicon grains 32a produced by annealing are not easily controlled.
Accordingly, the invention provides a method for fabricating a semiconductor capacitor of high capacitance. The steps of the method are easily controlled.
The method of the invention fabricates a capacitor electrode on a semiconductor substrate. The method includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through an interfering exposure step; and pattering the conducting layer using the patterned photoresist layer as a mask, thereby forming a capacitor electrode.
The method of the invention further includes forming a dielectric layer and an upper electrode, thereby forming a capacitor of a DRAM cell.